The present invention generally relates to a wafer level package having a multiplicity of IC dies formed thereon and a method for fabrication and more particularly, relates to a wafer level package having a multiplicity of IC dies thereon each incorporating dual stress buffer layers for I/O redistribution and a method for such fabrication.
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1Axcx9c1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under-bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion/diffusion barrier layer 30 and a wetting layer 28. The adhesion/diffusion barrier layer 30 may be formed of Ti, TiN or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UBM layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UBM layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, preferably at a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 42. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 nm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 nm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
The conventional flip-chip bonding process requires multiple preparation steps for IC chips, i.e. the formation of aluminum bond pads on the chip, the under-bump-metallurgy process on the bond pads and the deposition of solder required in the bumping process. The substrate that the IC chip is bonded to requires a flux coating in order to ensure an acceptable bond strength is formed between the solder bumps and the conductive elements on the substrate surface. The flip chip bonding process further requires a reflow process for the bumps, a flux cleaning process to eliminate excess flux material from the surface of the bump, a drying process after the cleaning process, an underfill process for dispensing an underfill material, and an underfill curing process to minimize thermal stresses in the underfill and in the joint formed.
The conventional method for depositing solder bumps described above presents a number of processing difficulties. For instance, in modern high-density semiconductor devices, the distance between I/O pads in a peripheral array continuously being reduced. In order to maintain a minimal required distance between the I/O pads, an I/O pad redistribution process must be conducted such that the pads can be transformed from a peripheral array to an area array. During the pad redistribution process, a plurality of metal traces must be formed to extend the I/O pads from the periphery of an IC die to the center of the IC die. It is desirable that, in order to assure the reliability of the die, a stress buffer layer is provided under the plurality of metal traces to buffer, or absorb, the stress incurred during the fabrication processes and to avoid stress cracking or fracture of the metal traces. The application of the stress buffering layers has been difficult in that if too thin a layer is applied, the stress buffering effect is insufficient to ensure the reliability of the IC die. However, when too thicker a layer of the stress buffering material is applied, numerous processing difficulties are incurred in the application process. Even though commercial stress buffering materials have been available in the marketplace, the fabrication technology for applying such materials to a satisfactory thickness has not been developed.
It is therefore an object of the present invention to provide a wafer level package that incorporates a stress buffer layer for I/O redistribution that does not have the drawbacks or shortcomings of the conventional wafer level packages.
It is another object of the present invention to provide a wafer level package that incorporates dual stress buffer layers for I/O redistribution that does not present any fabrication problems.
It is a further object of the present invention to provide a wafer level package that incorporates dual stress buffer layers for I/O redistribution wherein the layers are applied by a spin coating, a screen printing or a stencil printing technique.
It is another further object of the present invention to provide a wafer level package that incorporates dual stress buffer layers for I/O redistribution wherein a stress buffering material having a Young""s modulus of less than 6 MPa is utilized.
It is still another object of the present invention to provide a wafer level package that incorporates dual stress buffer layers for I/O redistribution wherein two separate stress buffer layers are first formed prior to the formation of a plurality of metal traces on top of the stress buffer layers.
It is yet another object of the present invention to provide a wafer level package that incorporates dual stress buffer layers for I/O redistribution wherein a first stress buffer layer and a second stress buffer layer are sequentially deposited onto an IC die each to a thickness between about 10 xcexcm and about 70 xcexcm.
It is still another further object of the present invention to provide a method for forming a wafer level package which can be carried out by depositing a first stress buffer layer and a second stress buffer layer sequentially by a technique selected from spin coating, screen printing, laminating, and stencil printing.
It is yet another further object of the present invention to provide a method for forming a wafer level package by incorporating dual stress buffer layers for I/O pad redistribution by forming a plurality of metal traces on top of two separate layers of stress buffer materials each having a Young""s modulus of less than 10 MPa.
In accordance with the present invention, a wafer level package incorporating dual stress buffer layers for I/O redistribution and a method for fabricating such wafer level package are disclosed.
In a preferred embodiment, a wafer level package that incorporates dual stress buffer layers for I/O redistribution is provided which includes a wafer that has a multiplicity of IC dies formed on an active surface; each of the multiplicity of IC dies further includes: a plurality of first I/O pads formed on a top surface insulated by a first dielectric layer deposited therein between; a plurality of interconnects formed on the plurality of I/O pads for providing electrical communication with the pads; a first stress buffer layer formed of an elastic material embedding the plurality of interconnects while exposing top surfaces of the plurality of interconnects; a second stress buffer layer formed of an elastic material on top of the first stress buffer layer without covering the exposed top surfaces of the plurality of interconnects; a plurality of metal traces formed on top of the first and second stress buffer layers each in electrical communication with one of the plurality of interconnects at a first end while a second end extends towards a center of the IC die; a second dielectric layer formed on top of the plurality of metal traces insulating the latter from each other while exposing a plurality of second I/O pads on each of the plurality of metal traces; and a plurality of solder balls formed on the plurality of second I/O pads arranged in an area array.
In the wafer level package that incorporates dual stress buffer layers for I/O redistribution, the first I/O pads are arranged in a periphery array and the second I/O pads are arrange in an area array. The first and second I/O pads are fabricated of a material that is selected from the group consisting of Cu, Al, Cu alloys and Al alloys. The first stress buffer layer may be formed of an elastic material that has a Young""s modulus of less than 10 MPa, the second stress buffer layer may be formed of an elastic material similar to that used in forming the first stress buffer layer. The first stress buffer layer and the second stress buffer layer may be formed to a thickness between about 10 xcexcm and about 70 xcexcm, or preferably to a thickness between about 30 xcexcm and about 50 xcexcm. The package may further include a UBM (under-bump-metallurgy) layer in-between the plurality of solder balls and the plurality of second I/O pads. The second stress buffer layer may be formed of a single protruded layer on top of the first stress buffer layer, or formed of a plurality of protruded layers on top of the first stress buffer layer.
The present invention is further directed to a method for forming a wafer level package by incorporating dual stress buffer layers for I/O pad redistribution that can be carried out by the operating steps of first providing a wafer that has a multiplicity of IC dies formed on an active surface; forming a plurality of first I/O pads on the plurality of IC dies insulated by a first dielectric layer deposited therein between; forming a plurality of interconnects on the plurality of I/O pads in electrical communication with the pads; depositing a first stress buffer layer of a first elastic material embedding the plurality of interconnects while exposing a top surface of the plurality of interconnects; depositing a second stress buffer layer of a second elastic material on top of the first stress buffer layer without covering the exposed top surfaces of the plurality of interconnects; forming a plurality of metal traces on top of the first and second stress buffer layers each having a first end in electrical communication with one of the plurality of interconnects and a second end extending toward a center of the IC die; depositing a second dielectric layer on top of the plurality of metal traces insulating the latter from each other; exposing a plurality of second I/O pads each on one of the plurality of metal traces; and forming a plurality of solder balls on the plurality of second I/O pads.
The method for forming a wafer level package by incorporating dual stress buffer layers for I/O redistribution may further include the step of providing the first elastic material and the second elastic material in a material that has a Young""s modulus of less than 10 MPa. The method may further include the step of depositing the first and the second stress buffer layer to a thickness between about 10 xcexcm and about 70 xcexcm; or preferably to a thickness between about 30 xcexcm and about 50 xcexcm. The method may further include the step of depositing a UBM layer on top of the plurality of second I/O pads prior to forming the plurality of solder balls on top. The method may further include the step of etching back a top surface of the first stress buffer layer to expose the top surfaces of the plurality of interconnects. The method may further include the step of exposing the plurality of second I/O pads arranged in an area array. The method may further include the step of depositing the second stress buffer layer in a plurality of islands of the second elastic material. The method may further include the step of exposing the plurality of second I/O pads by a photolithographic method. The method may further include the steps of exposing the plurality of second I/O pads by first depositing a plurality of photoresist studs on the plurality of second I/O pads, depositing the second dielectric layer on top and then removing the plurality of photoresist studs with the second dielectric layer on top exposing the plurality of second I/O pads.